Research On Enhance The Ability Of Fault-tolerant Technique Of Solid-State Disk

The solid-state storage is a new technology that attains high read-write speed by comparing Flash array. The increasing capacity of SSD(Solid-State Disks) is based on the increasingly capacity of single Flash chip. Nonetheless, the capacity of Flash chips increase at the expense of the decline in its reliability, which has become a bottleneck that restricts SSD commercialization. It is thus of critical importance to investigate SSD reliability and improve the development of solid-state storage technology. The research work of this thesis mainly focuses on bits reliability of Flash storage media and overall reliability of SSD.To date, the mainstream SSD typically employs NAND Flash as storage medium, as NAND Flash possesses advantages in high capacity and high access speed. With the increase of integration density, BER(Bit Error Rate) within NAND Flash is increasingly high, which requires powerful ECC(Error Correct Codes) to ensure the accuracy of the data. Low Density Parity Check(LDPC) code is one of the promising candidates. According to BER characteristics of MLC Flash, this dissertation proposes an organization method of the check nodes in LDPC codes. In specific, the BERs of most significant bit(MSB) and least significant bit(LSB) are distinct in MLC flash. Considering this issue, this dissertation proposes a new collocation method of MSB and LSB in check nodes of LDPC to reduce the decoding error probability. The simulated results demonstrate that the proposed method can effectively minimize the decoding error probability when there is a serious unbalanced MSB and LSB in the check node.In addition to BER problem, there would be failure of pages, blocks within Flash chips and even SSD controller. To solve the problems of pages and/or blocks failure, SSD typically utilize the Erase codes, and improve data reliability by introducing redundancy to some extent. This thesis propose a RAID-5 based modified SSD redundancy scheme, which can recover data from failure memory units if the failure is small than a channel level. Specifically, the proposed scheme employs a mapping table based on physical block address and partial delayed parity updating. In this way, the redundant mapping table and address mapping table are merged, which can thus reduce the occupation of RAM. Moreover, by optimizing the sequence of read operations, the influence of redundancy scheme on SSD performance is minimized and can thus accelerate the read operation.In the dissertation, Matlab simulations are designed and implemented to evaluate the decoding error probability of LDPC code considering distinct check nodes. Simulated results demonstrate that the proposed organization method of check nodes can achieve the minimum decoding error probability within every initial decoding error probability situation. In addition, the performance of designed redundancy scheme is evaluated employing SSDsim environment, with simulated results demonstrating that in addition to the aim of data recovery, the designed redundancy scheme can improve Flash's endurance by 13.6 % whilst reduce the average access time by 9%.