Design And Implementation Of A High Speed And Reliable Transmission Interface For Space Application

Complicated space environment greatly affect the accuracy of transmission in meteorological satellites and locating radars' data acquisition and storage systems, meantime,researchers have to deal with the growing amount of data. A high speed serial interface designed upon Aurora protocol which manipulates the high speed serial transceivers is the mainstream board level solution so far, unfortunately, the Aurora protocol does not make any assurances to the reliability of transmission, when gain the advantage of Aurora transmission rate, we can not guarantee the accuracy of the data. In the application of space environment, the probability of transmission anomalies increases greatly, therefore, improving the reliability of the transmission interface is very important. This paper presents improved methods based on error control technology, enhancing the reliability of high speed transmittal interface, which is capable to use in space applications.First of all, the thesis analyzes the correlative problems of high speed transmission interface for space application, after the study of different types of noise, the channel is modeled as an additive white Gauss noise channel, then two designs are provided to promote the reliability of the interface based on error control technology:1. The scheme bases on forward error correction technology. Begin with the channel model, it analyzes the applicability and performance of different error correcting codes, afterward constructs an appropriate QC-LDPC code and simulates its performance, an encoding and decoding arithmetic of the code is given too.2. The scheme bases on error detection and retransmission technology. After analyzing transmission logic and scalability of Aurora64B/66 B protocol and its IP core,the article redesigns the data transceiver module and adds the retransmission control logic, after that, a stop and wait ARQ method is achieved.Finally, in the 5th chapter, implementations and verifications of the two schemes are given. Scheme I uses embedded soft core to build a on-chip system which realizes the encoding and decoding processes of the QC-LDPC code. In transmission process,when setting the channel bit error rate 10-6and lane rate of Aurora64B/66 B core 5Gbps,the %EFS is equal to 99.68%, that means the transmission is reliable in 99.68% time after improvement scheme I. In the same bit error rate, when the maximum number of retransmission is 4 and frame length is 4096 bytes, scheme II is capable to reduce the frame error rate to 1.08 × 10-6. The results show that both two schemes are effective to strengthen the reliability of transmission interface. The former one has distinct data flow-control processes and does not require additional data frame buffer, however, the complexity processes of encoding and decoding algorithm unavoidably aggravated the transmission delay. The latter one only adds extra control logic to achieve stop and wait mode of retransmission by using CRC which is embedded in the Aurora64B/66 B core.But the restriction that the core could only works in duplex mode is inevitable.