Research On Software Defined Hardware Counters For SDN

Software Defined Networking(SDN) decouples control plane from data plane to make networks more flexible and manageable. In SDN architecture, to assist SDN controllers in obtaining global network statistics to manage entire networks and to support various applications(e.g., network measurement, intrusion detection, traffic engineering) upon the controllers, SDN switches need to maintain a great number of various statistic counters. However, existing SDN counters are typically implemented on ASIC and only support the passive statistical mode(i.e., counters report their values only when receiving requests). The implementation of these counters faces several serious challenges: 1) high memory consumption; 2) low flexibility; 3) low statistical accuracy. Facing these challenges of SDN counters, this paper proposes Software Defined Hardware Counters(SDHC) for SDN, which decouples the counter definition and implementation. This paper has these following main works and contributions:1. The concept and model of software defined hardware counters are proposed. Through dividing the processing of counters into three stages and implementing the management of counter definitions in software to control the behaviors of counters, SDHC decouples the counter definition and implementation, which effectively overcomes the problems of traditional implementation methods. Based on the idea of allocating counter memory on demands, SDHC effectively enhances the counter utilization to reduce the counter memory consumption. Through providing the flexible and convenient SDHC south-bound and north-bound interfaces, SDHC allows controllers to flexibly control counters, which enhances the flexibility. Besides, through introducing active statistics-reporting statistical modes, it can avoid statistical errors incurred by the accessing delay. This can effectively enhance the statistical accuracy.2. Key technologies of SDHC are studied thoroughly. Through studying the definitions and compression methods of messages between software and hardware, the transmission efficiency between software and hardware is enhanced, which reduces the requirement of transmission bandwidth. Through studying the classification and implementation methods of statistical modes, the updating-triggering based real-time mode and timer-triggering based timer mode are proposed, which can effectively meet the high-accuracy statistical requirements of various applications. Besides, the compression method of counter-value returning messages under the real-time mode is studied, which can avoid the high network bandwidth problem incurred by the burst of flow.3. The design of SDHC model is introduced in details. The functions and implementations of three modules are designed in details, which effectively enhance the processing efficiency of these modules to improve the entire performance of SDHC. Besides, through analyzing the behaviors of SDHC, SDHC south-bound and north-bound interfaces are designed in details, which makes controllers and applications flexibly control counters.4. The SDHC prototype is implemented and evaluated through several experiments and analysis. The results show that SDHC can provide high updating performance and statistical accuracy, and the updating latency incurred by SDHC is ignored compared with the transmission delay between controllers and switches.In conclusion, the paper proposes SDHC to overcome the problems of existing SDN counters. Due to its low memory consumption, high flexibility and high statistical accuracy, SDHC has theoretical significance and practical value for the design and implementation of SDN switches.