Design, Optimization And Verification Of The Floating-point ALU For The 32 Bit High Performance M-DSP

M-DSP is a high-performance multi-core DSP with 32-bit bandwidth and 1.1 GHz clock speed independently developed by microelectronic research institution of National University of Defense Technology. The M-DSP is mainly used in the civil field including speech synthesis, image recognition and wireless communication, also in the military field including radar, sonar, search and anti-search. Its main target is to promote the self-independence of military information and improve the development of high-performance multi-core DSP. Based on the study and development of the M-DSP kernel, this paper mainly completed the design, verification and optimization of the Floating ALU(Arithmetic Logic Unit) inside the kernel. The concrete content includes the following aspects:1. Based on the performance requirements of the floating-point arithmetic, we designed the instruction set and did module partition for the Floating ALU of M-DSP, analyzed and realized the key algorithm used in the sub-module. On the basis of traditional dual-channel algorithm, the rounding merger processing mechanism was added to meet the requirements that float double-precision addition should be done within 5 clock cycles. The design of floating-point instruction transformation was accomplished by applying the algorithm which merges the operations of complementation and the later rounding judgement.2. According to the existing verification methods of IC design, we made sufficient verifications of floating ALU from two aspects of simulation verification and formal verification, also did the statistical analysis of coverage rate. The simulation verification was made from two aspects of module-level verification and system-level verification. The formal verification was completed with the help of ATEC and Formality. The results of coverage rate show that the floating ALU in M-DSP has met the requirements of coverage rate and the verification work was complete.3. Logic synthesis and optimization were also done to the floating ALU in M-DSP under 45 nm CMOS process by adopting Design Compiler. After analyzing the synthesis report, we made timing optimization to the critical path of floating ALU by applying the methods of module-cutting, logical structure adjustment, preferred processing the key signals, pipelining logic-partition, and made area optimization to it through module reuse. Delay was reduced by 100 ps and performance was improved by 16.8%, eventually reached design objective of 1.1 GHz.