The Design Of Analog Front-end Circuits For Passive UHF RFID Tag

RFID(Radio Frequency Identification, RFID) is a kind of technologies to realize the object recognition and data communication without contacting, through the near field of inductive coupling or far-field electromagnetic wave propagation.Widely used in the Internet of Things, logistics management, anti-fake and anti-theft,etc.In order to meet the demand of practical application which requires low cost, low power consumption and high performance, this papermainly studied energy harvesting and management and modulation and demodulation circuit.First of all, this papershowed the chip architecture ofUHF RFID tag and design difficulties and performance parameters of thepassive tag chip.Next, starting from analysis of ultra high frequency energy links, in contrast to the charge pump structure inliterature, puts forward a new kind of threshold compensation charge pump structure;While designed LDO circuit which is suitable for low input voltage, low power consumption;Designed the power-on-reset circuit providing reset signal for digital circuit;Used a local clock ring oscillator circuit so as to reduce the power consumption of the chip, and joined the digital calibration technology of clock frequency.And then put forward a demodulation structure which is compatible with ultra high frequency international standards and domestic standardsandused voltage mode as well as envelope detector and enabled circuit,had a characteristic of high sensitivity,low power and low demodulated error. PSK modulation circuit is designed.So that UHF RFID tag could receive more energy.Finally, based on UMC 0.18 ?m EEPROM process, the simulation results of each circuit module showed, as well as layout.Charge pump can rise to 1.83 V while the input voltage is 500 mV.LDO can stabilize the output voltage of 1.1 V, power on reset circuit provides a reset signalwhen LDO is stable, the clock circuit produce 3.84 MHz clock frequency, clock error is less than ± 2%;Demodulator support the international and domestic standards, modulator use PSK modulation; The core area of analog front end of Chip is 533 um * 817 um, power consumption is 4 ?A.