Hardware Trojan Prevention Based On Fully Homomorphic Encryption

With Integrated Circuits(ICs) design and fabrication go globally, it suffers the threat of malicious modification which may lead to unexpected results. The malicious modification of an electronic circuit or design is called Hardware Trojan(HT). As ICs are the foundation of information technology, the HT poses a great threat to the security of it, which makes the HT catches more and more attention and becomes one of the hot research topics.Researchers usually focus on the detection of HT. However, detection is a passive measurement after the target IC has been fabricated. A better way is to take the initiative to stop HT implantation from the beginning. We propose a HT prevention scheme composed of three modules, namely trusted encrypt module, trusted decrypt module and untrusted chip module. The encrypt and decrypt modules are totally under our control and secure, but the chip module may be designed or fabricated through third-party and thus possibly insecure. The core concept of the prevention scheme lies in the separation of the chip module so that it can only access and process encrypted data from the encrypt module. Without the decryption key, the HT does not know how to attack the data.As to the implementation of the prevention scheme, we need to utilize Full Homomorphic Encryption(FHE) encryption to achieve it. FHE allows us to compute arbitrary functions over encrypted data. It consists of four algorithms, namely key generation, encrypt, decrypt and ciphertext evaluation algorithm, in which encrypt, decrypt and evaluation algorithm correspond to the encrypt, decrypt and chip module of the prevention scheme respectively. Specifically, we adopt a lightweight FHE library named FHEW which is based on Learning with Error(LWE) problem. The LWE problem has been proven as hard as certain worst-case lattice problems.In order to verify the feasibility of the prevention scheme, we simulate the hardware Trojan prevention scheme with System C. The experimental results of two case studies on 8-to-1 multiplexer and 8-bit full adder prove the feasibility of the scheme.