Design And Verification Of AES Algorithm Based On AMBA Bus

The security of information has become more and more important with the development of the information industry. In addition, with the development of portable devices and mobile terminal some new requirements are put forward to the hardware implementation of cryptographic algorithms, such as small area, low power consumption, etc. AES is a new generation of data encryption standard and is widely used in the information security. In view of above situations, this thesis proposes an novel AES encryption algorithm implementation scheme which supports different key length, and is compatible with AHB bus.In order to reduce the area, a 32-bit data path structure is proposed by sharing operation blocks between encryption and decryption as well as between round function and key expansi module on. For AHB bus interface module, this thesis illustrates its implementation structure and analyzes the logic function. In the design of data path module, a method to implement the data storage which can handle the shiftrows tansformation is proposed, and the scheme to implement the invmixcolumn module is discussed according to the function and area demand. Then based on the analyze of the key expansion algorithm, this thesis proposes a circuit structure which can support forward and reverse key expansion suitable for 128, 192 and 256 bit key length, and analyzes the two implementation methods of Rcon function and the applied occasions. Then this thesis analyzes the structure of subword module and introduces the method to implement the sbox. In the final this thesis analyzes the method to implement the state machine control module. First the control signal in the design is listed and the encryption/decryption process table is given; Then the generation of control signals according to the table as well as the optimization method is described; Then state machine coding method is studied and the hybrid coding scheme is proposed; The last is the implementation method about operation mode configurability.This design adopts the Verilog RTL level description and has passed the logic function simulation. The FPGA implementation result shows that it consumes 3231 slices, the clock frequency can reach up to 88 MHz, the total power consumption is only 0.421W. Finally, the design completes board testing which ensures the correctness of the design. The design of AES module has the comprehensive function and reliable performance and is suitable for portable devices which requires high speed, small area and low power.