Research And FPGA Design Of Signal Synchronization Technique For Satellite-based Augmentation System

The Global Navigation Satellite System(GNSS)has found wide application in many fields of society. However, the quality of service can not meet the demand in some special occasions.So it is necessary to carry out the research on the satellite-based augmentation system(SBAS). Synchronization is the key problem to directly affect the system performance. In this thesis, we study the signal synchronization technique in SBAS, and the main work and achievements are as follows:1.The fast acquisition technique of weak signal is studied. Both the serial liner searching method and the parallel code-phase searching method are analyzed, including their acquisition probability and time. We propose an improved high accuracy parallel acquisition mothed, by taking the quadratic interpolation algorithm to improve the accuracy of frequency estimation. The simulation results show that the acquisition probability can reach 95% when SNR is-25 d B.2.Two kinds of carrier tracking scheme are designed for high dynamic applications. The first one is integrating second order FLL and third order PLL. The detailed parameters of the tracking loop are given, and the influence of the non-coherent integration time on tracking performance is analyzed. The second one is Kalman filter-based carrier tracking scheme. The Kalman filter gives the estimated values of frequency offset and its changing rate, which can help the PLL to realize accurate carrier synchronization. Simulation results show that both schemes can obtain favourable tracking performance in the case that SNR is-25 d B and the changing rate of frequency offset is 400Hz/s, which can meet the requirements of carrier synchronization in the SBAS.3.The DLL based code synchronization technique in the case of low SNR is studied. Simulation results show that reliable tracking of PN code is realized when SNR is-25 d B.4.The FPGA design of main signal synchronization modules in the SBAS is implemented, including FFT-based parallel code phase search acquisition, Costas loop and delay locked loop. We make improvements to the acquisition method to save hardware resources. The average sampling approach is introduced to reduce the length of FFT algorithm, which further saves the hardware resources. The simulation results have verified the correctness of each module.