Hot-Carrier Effect Of NMOSFET

With the rapid development of VLSI, the requirement to improve the reliability of the whole circuit system and a single device is very urgent. IC is composed of components, and the performance and quality of the individual devices directly determines system reliability. As one of the important reliability issues, hot carrier injection could destroy the quality of the gate oxide layer and life with high intensity electric field. It is of important significance to study on hot carrier effect, because the hot carriers will cause parameter degradation and affect the stability of the circuit system.In this dissertation, hot carrier injection and SILC degradation on NMOSFET are researched. First the basic physical mechanisms and generation mode of hot carriers on NMOSFET are introduced. Based on this some classic physical models are analyzed in detail. Classic physical models include substrate current model and lucky electron model respectively focus on substrate current and gate current. Then research methods which are popular domestic and overseas about HCI are introduced, and focus on the simulation software Silvaco Combined with simulation results by Silvaco TCAD.a group of NMOSFETs with different structural parameters were measured to study the substrate current and gate current characteristics. The worst HCI stress condition is determined, and it is closely related and structural parameters. Effect of channel length to Worst Vg and the physical mechanism are analyzed. NMOSFET parameter degradation includes Vth, Idsat, Gm and SILC under HCI stress is studied by intermittent stress test. In order to prove SILC degradation is caused by HCI, some experiments are designed to explore the relationship between SILC degradation and threshold voltage shift as well as maximum substrate current. Experimental results show that HCI is the key factor to lead to SILC drift, and correspondingly gate leakage current under HCI could be important characterization to HCI damage. It is noted theoretically that there is some experimental error during intermittent stress test. Therefore uninterruptible stress experiment is designed and it is found that recovery of device performance during intermittent stress test is indeed existed, which provides effective ideas and methods for the recovery of HCI damage.