Design And Implementation Of Digital Channelizer For On-board Flexible Transponder

As one of the key techniques in broadband satellite communication system, the digital channelization technique can extract the narrow band signal of each user in the uplink channel effectively and reconstruct the required downlink signal after the on-board processing operations while the satellite's payload structure keeps unchanged. The digital channelizer based on the flexible transponder is investigated emphatically in this thesis. This channelizer is able to exchange the non-uniform broadband signal as well as the uniform bandwidth signal. Moreover, it also has the features of simple and efficient structure, good flexibility and high capacity. The main work of this thesis is summarized as follows:1. Based on the analysis of the complex exponential modulated filter bank and the polyphase decomposition technique, the highly efficient architecture of digital channelizer is proposed. This architecture is capable of completing the on-board processing operations such as splitting, switching, combining. Furthermore, it has a low implementation complexity.2. In view of the special demand for reconstructing the signals in the non-uniform bandwidth digital channelizer, a novel design algorithm of the prototype filter for digital channelizer combining the frequency sampling method and window function method is proposed to decrease the reconstructed signal distortion and reduce inter-channel leakage. Simulation illustrates that this algorithm can enable the prototype filter to have the larger stop-band attenuation and the lower pass-band stitching jitter.3. A simulated model of the non-uniform bandwidth digital channelizer is set up for assessing and analyzing the performance of the non-uniform bandwidth digital channelizer. Then, in case of the different modulations(BPSK, QPSK and 8PSK), the simulation performance is evaluated in terms of the power leakage between the adjacent sub-channels, the BER and the quantization error's influence. Simulation results show that the leakage power between the adjacent sub-channels is less than-90 d B, and that the performance degradation of the digital channelizer is less than 0.2d B compared with the ideal case when the value of the BER is 10-3.4. The numerical control AGC circuit is proposed to compress data amplitude range. Because the switching module and D/A module in the digital channelizer has certain restrictions on the data-width of the required switching signal, the AGC technique is adopted in the both modules to make the input signal stable in a certain dynamic range, which further ensures that both of them work properly. Simulation illustrates that the numerical control AGC circuit satisfies the system requirement and has little impact on the performance of the non-uniform bandwidth digital channelizer.5. The FPGA design and implementation of the non-uniform bandwidth digital channelizer is completed. The overall design scheme of the digital channelizer is presented at first; And then, a novel FPGA designing approach of the filter is also proposed in order to reduce the filter hardware implementation complexity; Finally, the FPGA design and implementation of each sub-module in this digital channelizer are provided. The results show that the digital channelizer merely needs 256 multipliers, which greatly reduces the hardware resource demands.