High-speed Data Transmission Design And Implementation Based On FPGA

With the shortage of radio spectrum resources, it's an urgent matter to seek a new communications technology to improve spectrum utilization ratio. The adaptive transmission technique has been gotten extensive research because of dynamic matching channel conditions to make the throughput approaching channel capacity, which lead good spectrum efficiency. The adaptive transmission system studied by our group is based on satellite and ground station to transmit data for the application scenarios, and this is realized with no rate code and hybrid automatic retransmission technology. In the adaptive system, two pieces of decoder board, which contains 6 FPGAs, are used for decoding with no rate code. Data transmission interface between host and decoder board is a bridge between them and its performance affects the system stability and throughput directly. The purpose of this paper is to research and design the high-speed data transmission interface circuit between the host and decoder board and the high-speed data transmission interface circuit decoding board between the FPGAs. At last the 300 Mbps decoding throughput of system can be satisfied.This paper introduces research studies of the adaptive transmission system based on no rate code, and the decoder board used in the receiving platform architecture and system are also introduced. The 300 Mbps decoding throughput of system are analyzed, and two pieces of decoder board are used for decoding simultaneously. Because of the decoder board has the working characteristics of short decoding cycle, polling way is employed to improve the efficiency of cooperation between the software and hardware. PCI Express(Peripheral Component Interconnect Express) bus is used for data transmission between the decoder board and PC, at the same time, high-speed serial data transmission between FPGAs is realized by the link based on Aurora 8B/10 B protocol, achieving the management of collaborative decoding between FPGAs.Finally, the correctness of the design are verified. The decoding throughput of two pieces decoder board can reach 313.2 Mbps and this can satisfy the system demand of decoding throughput.