Research On Design Approach Of Mitigating Soft Errors For On-board Software Based On Zynq-7000

In recent years,commercial-off-the-shelf(COTS)FPGA has been increasingly used in the aerospace field because of its low cost,high performance and no restriction on foreign imports.Among them,Xilinx Zynq-7000 series So C FPGA integrates ARM Cortex-A9 MPCore processor,programmable logic and hard IP peripherals in the same chip,it has attracted wide attention in the field of small satellites because of its perfect combination between flexibility and configurability.However,as a COTS device,Zynq-7000 has low radiation resistance.It is susceptible to radiation from various high energy par ticles and rays in the space environment,resulting in soft errors which are caused by transient fault such as single event upset(SEU).Soft errors affect the normal operation of software through the on-chip memory and off-chip memory in Zynq-7000,so that it causes a confused order or a wrong result to software operation,it will bring unpredictable damage to the system.In order to solve the problem of fault detectio n and recovery for onboard software when soft errors occur,the research on design approach of mitigating soft errors for on-board software based on Zynq-7000 is carried out in this article.The article presents a two-level fault-tolerant design mechanism on Zynq-7000 So C,which uses Xilinx ZC702 and Vivado 2015.4 as the hardware and software development platform,combines the hardware tolerant resources in Zynq-7000 and classic software tolerant methods from the demand on mitigating soft errors.On the basis of the above overall fault-tolerant design,each fault-tolerant module in the two-level fault-tolerant mechanism is designed and implemented in detail.For the data-flow error and control-flow error caused by the on-board software,dual-core check and rollback recovery are adopted as the first level fault-tolerant mechanism,which combines with the redundant structure in the dual-core processor of Zynq-7000,software implemented EDAC and triple modular redundancy(TMR)for dataflow error as well as exception trap and watchdog for control-flow error are adopted as the second level fault-tolerant mechanism,so as to implement the detection and recovery of soft errors.In order to verify the validity and reliability of the fault-tolerant design method,the article designs and implements the soft errors fault injection and verification software,which has the capability for convenient human-computer interaction,and injects the fault to the fault-tolerant module and fault-tolerant on-board software respectively using the software fault injection method based on int errupt.The experimental results show that compared with no fault-tolerant or single-core faulttolerant mechanism,the two-level fault-tolerant mechanism based on the dual-core processor of Zynq-7000 has the better soft errors detection and autonomous recovery capability to mitigate soft errors.The design approach provides an effective mitigating soft errors solution for So C FPGA space application,also provides the key technology for SoC FPGA to promot e and use in the field of small satellites.