Implementation And Verification Of Time-triggered Communication Bus In Train Control Safety Computer

With the rapid development of China’s high-speed railway in recent years,more and more people choose high-speed rail as a major way of travel,which puts forward higher safety and reliability requirements for train control system.As a key component of the train control system,the train control safety computer is responsible for handling the core data of train control system safety application.The communication bus is regarded as "neural network" of the safety computer platform,which guarantees reliably communication of each functional unit in the safety computer.In this paper,the communication bus of safety computer platform adopts time triggered communication bus according to the relevant international standard of safety communication.Its research is of great significance for implementing general-purpose computer of next generation train control.In this paper,the time-triggered communication bus is designed according to the actual requirements of the train control safety computer platform.The physical layer of the bus draws on the characteristics of ARINC659 bus,and a more reliable,flexible and scalable bus is designed.A synchronization management mechanism is proposed to ensure the synchronization of clocks of multiple communication nodes in the data link layer.At the same time,a communication scheduling algorithm of multi-master polling is proposed to ensure that each communication node sends messages at a fixed time.In the process of data transmission,the error control strategy,which is mainly divided into two aspects,one is error detection to determine whether the current data frame is correct and the other is an improved retransmission mechanism to achieve error control.The data of the link layer is encapsulated into a fixed format data frame,which facilitates the transparent transmission and data verification.Secondly,the deterministic and stochastic Petri Net is selected to use for formal analysis by analysing and comparison of different formal modeling methods,combing with time-triggered bus concurrency and time deterministic characteristics.It is proved that time-triggered mechanism can effectively protect various risks of bus communication by analyzing the protection measures adopted by the communication bus against and establishing the fault model of the bus.At the same time,the real-time performance of retransmission mechanism for time-triggered bus is analyzed by comparing the reliability and delay of different retransmission times.The number of bus retransmissions is determined to be at most 3 times.Finally,framing module,deframing module,time management module of time-triggered mechanism and serial-to-parallel conversion module of the bus data link layer are implemented by Verilog HDL programming language.In the process of implementing the program,Modelsim software is used for simulating each various functional module to observe whether the timing diagram is correct.In the board-level verification,logic analyzer SignalTapⅡ is used to capture the timing diagram of FPGA internal pin to observe whether the time-triggered bus is running.In this paper,formal modeling and physical simulation method is adopted to verify whether the time-triggered communication bus meets the requirements of railway signal safety communication.At the same time,the realization of bus IP core improves the portability and expansibility of communication bus,which ensures that it is suitable for different platforms.It provides the basis for the implementation of general-purpose train control safety computer.