Design Of Low Power Oscilloscope Based On Time-interleaved Technology

The oscilloscope,playing an indispensable role,was widely used for signal analysis and measurement.With the rapid development of technology,the DSO(digital storage oscilloscope)gradually replaced the analog one due to its performance improvement.However,as a branch of oscilloscope,the portable DSO was widely used in some special applications,which overcomes a series of shortcomings of normal DSO,such as bulky,high power consumption and non-portable.It’s very important to increase the sampling rate for DSO to meet the requirements of real-time capturing and measuring of complicated wide-band signal.Nowadays,time-interleaved technique is the most suitable method to increase sapling rate,through which we could break through the limitation of the conversion rate of single ADC(analog-to-digital)chip and realize high-speed data acquisition system.Although the sample rate is increased by time-interleaved technique,the performance of TIADC(time-interleaved ADC)is decreased by mismatch errors and timing skew error.Therefore,the task of this subject is divided into two parts.At first,a portable low-power DSO will be designed based on FPGA in this subject.Secondly,the mismatch errors will be estimated and calibrated to improve the SFDR(spurious-free dynamic range)of system.Details are as follows.First of all,the model of TIADC system is built according to the structure and principle of TIADC system.Under the actual application scenario,the sources and causes of mismatch errors are analyzed.And according to the mathematical model obtained,the output spectrum characteristics of TIADC in different cases are analyzed.Furthermore,a complete set of methods are proposed for removing the distortion created by mismatches in TIADC.The method is divided into two parts including estimation for mismatch errors and compensation for mismatches.The estimation of the mismatch is accurate and keeping low the complexity of the associated algorithm.The compensation for offset and gain mismatch errors uses estimated parameters while the correction for timing mismatch errors uses the simplified Lagrange interpolation method.The proposed compensation is a single-precision floating-point structure which is simulated under the severe mismatch condition(up to 5%offset and gain mismatch and 10%leading or lagging timing mismatch).The result is that it corrects the severe mismatch errors in TIADC and the spurious-free dynamic range of sampling sequence is developed up to 53dB after compensation.Besides,there is no limitation on the number of channel converters for the compensation structure.Finally,based on a single FPGA chip,a portable low-power DSO are developed.In order to meet the requirement that the dynamic range of input signal is wide,the analog front-end circuit with flexible gain is designed.Due to the dual-channel ADC structure and time interleaved technique,the sampling rate of DSO is doubled.The problem of recovering the waveform is solved by sine interpolation method after analyzing a variety of interpolation strategy when the sampling point is insufficient.