The Research And Implementation Of Serial Buses Decoding And Triggering Technology Based On FPGA

With the rapid development of modern communication technology, due to low cost, strong anti-interference ability, far transmission distance, serial bus get more and more widely used. In the actual process of debugging, serial bus measurement in the way of trigger, bus type, versatility and the correctness of the protocol decoding analysis have put forward new requirements to test equipment. Digital phosphor oscilloscope is indispensable and comprehensive measuring instrument in modern test system. Serial bus decoding and trigger technology has become the key technology of a digital oscilloscope accurately capture the serial bus trigger signal and stability show the waveform data.This topic belongs to the senior trigger and part of the protocol analysis module in digital phosphor oscilloscope. Mainly serial bus decoding of digital phosphor oscilloscope and trigger technology was studied and the implementation. Based on the research of basic triggering technology principle in digital phosphor oscilloscope and serial bus protocol standard, combination of top-down design ideas, based on Xilinx Kintex-7 series FPGA chip to realize the CAN and LIN two serial bus decoding and trigger function of modular design.Paper first introduces the project development based on digital phosphor oscilloscope platform and the FPGA chip. And then expounds the serial bus decoding and the overall design scheme of trigger module and the block diagram. Then the paper introduces the detailed design and implementation of decoding parameters register module, serial bus decoding module, trigger discriminant comparison module, decoding tags generated module and decoding data storage and transmission module. Finally do the test and verify in detail for the design of the paper, on the independent hardware platform of digital phosphor oscilloscope. This article research results has been successfully used in digital phosphor oscilloscope prototype, achieve the expected function and index system.