A High-speed Data Test System For CMOS Silicon Pixel Detector

European Organization for Nuclear Research(CERN)announced the discovery of the Higgs particle at the Large Hadron Collider(LHC)in 2012.This Higgs particle provides the most promising explanation of the origin of the particle masses under the framework of the "Standard Model".However,the nature of the particle has not been fully understood yet.The Chinese High Energy physics community has proposed the Circular Electron-Positron Collider(CEPC)to measure the Higgs properties with high precision and might find clues of "new physics" by catching any deviations from the Standard Model predictions.To achieve the required high precision,the CEPC vertex detector must be constructed with pixel technologies featuring high spatial resolution,low mass and low power consumption.Such stringent requirements would make the CMOS silicon pixel detector an extremely promising candidate.To characterize the CMOS pixel detector being developed for CEPC,a high-speed data acquisition system must be designed.We propose to build this system based on high performance FPGA and transmit data via PCI Express.The effective data transmission speed has been measured up to 6 Gb/s.It has also demonstrated its low bit-error when operating at high speed.Overall,the test system design satisfies the most crucial requirements and can be further developed for CMOS pixel detector characterization.