High Density And Precision Time Measurement Method For CBM-TOF Super-module

Particle flight time measurement is indispensable in modern high energy physical experiments as it can reflect the momentum and mass of particle indirectly,which is important for revealing the interaction and physical property of particles.Nowadays,high energy physical experiments have the development characteristics of high particle energy,numerous detector channels and high data rate,which put forward higher requirements for time measuring resolution and data reading ability.The Compressed Baryonic Matter(CBM)experiment is fixed-target experiment which will operate at the future Facility for Antiproton and Ion Research(FAIR)in Darmstadt.The goal is to explore the QCD phase diagram in the region of high net baryon densities using high-energy nucleus-nucleus collisions.Time-Of-Flight(TOF)system,one of the detectors of CBM experiment,aims at identifying hadrons.CBM-TOF is composed of super modules containing high resolution Multi-gap Resistive Plate Chambers(MRPCs),and there are over 100,000 readout channels in total.The TOF wall can be subdivided into two regions as inner and outer wall according to event rate level,and the maximum event rates per channel are up to 500 kHz and 300 kHz respectively.The required full TOF system time resolution is of the order of 80 ps,and resolution of TDC should be better than 25 ps per channel.At present,development of MRPC detectors for CBM-TOF is still in progress.In order to meet the requirement of quality evaluation of a super module detector,this thesis implements a 320-channel time digitizing electronics system for high density and resolution time measurement.This front-end system based on"sandwich" structure is also able to readout the 320-channel data according to self-defined protocol and transmit the data to back-end readout crate.The content of this thesis is organized as follows:Overview of CBM-TOF experiment is introduced in the 1st Chapter,as well as two mainstream time digitizing technologies,ASIC TDC and FPGA TDC.Scheme of a high density time measurement and data readout base on sandwich structure are introduced in the 2nd Chapter.The 3rd Chapter details the implementation of 32-channel TDC based on FPGA and the functions of edge measurement,TOT measurement and trigger match.The 4th Chapter details the implementation of 320-channel front-end readout electronics,including distribution of high performance clock and trigger signal,high speed data transmit link and self-defined protocol design.Tests of 32-channel TDC and the high speed data transmit link based on Xilinx transceivers are presented in the 5th Chapter.A conclusion of this thesis is drawn in the 6th Chapter as well as an outlook of future work.