The Design Of Four-channel Receiver In 0.5T MRI System For Joints

MRI(Magnetic Resonance Imaging)instrument,which is based on magnetic resonance imaging theorems and technologies,is significant at tissue lossless imaging field.After four main development phases,it is now widely used in scientific research and medical treatment,beneficial to country's bloom and people's livehood.Although China is the most important market of MRI instrument,the referenced R&D ability in China still lags behind advanced international level.For the sake of changing this circumstance,China steps up efforts to it.The four-channel digital receiver,which this dissertation pays attention to,is a key component of the“0.5T MRI system for joints”.It is constructed with the SDR(Software Defined Radio)framework,conveninent for miniaturization and digitalization.The main body consists of a clock module,an AD6620 subsystem,a DSP(Digital Signal Processor)subsystem and a FPGA(Field-Programmable Gate Array)subsystem.These subsystems above are connected with each other by several serial ports.Some digital signal processing techniques,such as pass-band sampling,digital quadrature detection and CIC(Cascaded Integrator-Comb)filter,are adopted.The clock module is built of a clock-programmable chip and two clock fanout buffers and the related Printed Circuit Board(PCB)is designed to conform to Electromagnetic Compatibility(EMC).It is drove by a unique oscillator,outputting multi-path single and differential clocks with the same phase but different levels.The AD6620 subsystem,which is majorly used to detect the Free Induction Decay(FID)signals by digital quadrature detection and then to decimate the obtained digital base-pand signals,is made up of four channels.The main work is to decide registers values and code configuration software,making this subsystem run in single channel real and serial output modes and then generateing low rate in-phase and quadrature digital signals.The DSP subsystem is mainly utilized as a second decimator to further decrease the rate of signals from AD6620.A comprehensive design needs the following steps:simulating CIC filters and compensation filters with MATLAB,coding referenced DSP programs and validating the result of the frequency-response characteristic.This subsystem recepts and processes data from diversity AD6620s by Time Division Multiplexing(TDM),obtaning lower rate in-phase and quadrature digital signals than before.Benefiting from the harmonic working of hardware logics and the SOPC(System on a Programmable Chip),the FPGA subsystem is employed to control the whole system,configure chips,receive data from DSP and so on.A multi-channel selector is used to separate data from different channels and store them into corresponding partitions.These data are ultimately uploaded to an upper monitor.