Low Harmonics Distortion Multi-bit Interface For ΣΔ MEMS Accelerometer

Currently, switched capacitor micromachined accelerometer has very high researching value domestic and international. Because of its many advantages, capacitive accelerometer has good application prospects in fields of military and civilian. Using ΣΔ modulator module can directly obtain the digital output signal. Since the harmonic distortion has great influence on the system SNR, low harmonic distortion accelerometer can improve the accuracy of the system. The technology of quantization can reduce the quantization noise by reducing the quantization error. Through reducing the harmonic distortion and taking multi-bit quantization, from these aspects this paper carry on the design of ΣΔ capacitive accelerometer.Based on the investigation of the accelerometer domestic and international trends, this paper analyzes the working principle of the accelerometer system and its each module. Then it makes quantitative analysis for the interface circuit noise and mechanical noise for the main noise of accelerometer system. And it makes quantitative analysis for the circuit nonlinear source The accelerometer header chooses vacuum packaging. It can obviously improve the mechanical noise. The interface noises are affected by the switch resistance, operational amplifier and reference voltage source. To reduce the noise of operational amplifier can increase tube of the input transconductance. In the preceding stage of detecting circuit, adding CDS technology can eliminate 1/f noise and offset. Aim at nonlinear, optimizing system parameter and improving loop gain can effectively decrease the nonlinear.The structure of accelerometer is feedforward structure which has local negative feedback. It improves the low-frequency gain and nonlinear. Adding to the pre-phase compensator structure in the system can compensate the phase loss which results from high Q sensitive structure and high order system. It thereby enhances the stability of the system. Using MATLAB constitutes modeling for the fourth order accelerometer which is consist of sensitive structure and modulator. Simulate three different situations for one bit quantization, multi-bit quantization and considering mismatch. By the power spectral density of the output signal, the signal noise is about-155 d B, SNR is 128.9d B, effective number of bits is 21.11 bits.Based on the optimizing results of the system-level modeling, using 0.35μm CMOS process designs each transistor-level circuit. Considering the mismatch of multi-bit DAC, using Modelsim tools designs for the data weighted averaging technique(DWA) algorithm. Finally, simulation in Cadence Spectre Verilog environment, SNR is 104.3d B. ENOB is 17 bits. The output signal noise less than-135 d BV/Hz1/2. The noise density is 178ng/Hz1/2The harmonic distortion is less than-110 d B.Finally, draw the analog circuit layout. Combing analog circuit layout and DWA module digital layout can obtain the output signal of the accelerometer SNR 102.6d B. ENOB is 16 bits.The harmonic distortion is less than-110 d B.