Study On Extraction Parameters And Degradation Under Electronical Stress Of IZO TFT

In recent years, with the rapid development of elcetronic information industry, display technology based on thin-film transistor also has been considerable progress. Currently the main bottleneck is the degradation of device under electrical stress, which restricts its application in the field of flat panel display. Therefore, investigation of the IZO TFT degradation characteristics under various electrical stress has practical value and scientific significance. In this work, deep studies on parameter extraction and degradation mechanism under electric stress were researched. The main contents and results are as follows:(1) The mainly electrical parameters of the IZO TFT were extracted inculding density of states and interface state density as well as threshold voltage, sub-threshold swing, effective mobility. By multi-frequency C-V and the channel resistance method, the drain and source contact resistance was extracted; Besides, source and drain contacts resistance extracted by transmission line method(TLM) is 1.45 MΩ,which is close to that of the channel resistance method(CRM). Further, by using RC network and multi-frequency C-V method, the density of states(DOS) in the active layer was extracted, and the parameters of acceptor-like trap was fitted. In addition, the interface state density of the IZO TFT was investigated by 1/? noise, and the value is 1.01×1018 cm-3eV-1.(2) The degradation characterization of the IZO TFT under gate voltage stress was investigated. The results show that the device degradation under the gate voltage is mainly manifested as the shift of threshold voltage. Under the negative gate voltage stress, the threshold voltage has a positive shift, while under the positive gate voltage stress, the threshold voltage shifts toward the negative direction. The reason is that electron is injected into insulator under the negative-bias stress, while hole is injected into insulator and new defect is generated under the positive-bias stress. Meanwhile, 1/? noise analysis further validates the correctness of the above mechanism.(3) The characterization of IZO TFT under simultaneous gate and drain bias stresses were investigated. The results indicated that the electrical characterization of the device shows a significant degradation. The increase of the threshold voltage and the decrease of the sub-threshold slope are mainly due to the hole injection and generation of new defect states.(4) The characterization of IZO TFT under electrostatic discharge was investigated. The results show that a breakdown voltage in the long channel IZO TFT only depends on the stress level rather than the stress width. It is finally assumed that hard failure is induced by the gate dielectric catastrophic breakdown instead of the thermal process and breakdown voltage is approximately in line with the human body model(HBM). Besides, TPL stress will lead to the transfer curve with a negative shift, which is due to holes captured by the gate dielectric and a large number of new defect states. Based on the TLP stress with different pulse duration experiment, the function relationship between damage voltage and pulse width is deduced.