Low Power Digital Circuit Design Based On Amorphous Oxide Semiconductor Thin-Film Transistor

Amorphous oxide semiconductor(AOS) has the advantages of higher mobility, higher sub-threshold slope and higher on/off current ratio when it is compared to a-Si. Besides, it has the advantages of good uniformity and low fabrication cost when it is compared to Poly-Si. Amorphous oxide semiconductor is being investgated for Radio-Frequency Identification(RFID). Currently, the performance of complementary devices is not consistent yet. Therefore, the complementary circuit cannot be adopted and the power consumption of RFID tag will thus be greater. Reducing the power of digital circuit contributes to greater sensing distance, larger circuit scale and better system stability. This paper made effort to reduce the power of RFID tag of amorphous oxide semiconductor from three aspects:1)In regard to monotype inverter, the Pseudo-CMOS inverter is analyzed and the width of key drive transistor is optimized to reduce the maximum quiescent current, the gate area of input transistor and increase the rise speed; A Re-Pull-Down transistor scheme is proposed to improve the Pseudo-CMOS inverter. In the new circuit, two transistors are added and the cutoff voltage of the output transistor is lower in order to maintain the ratioless feature.2)In regard to the decoder circuit, monotype complementary gate is utilized to improve the decode scheme of counter + monotype nor gate. The monotype complementary gate has the advantage of low quiescent current when being driven with complementary input signals. And the output signals of D flip-flop are complementary signals which have not been fully utilized in the shift-chain scheme. By utilizing the complementary signals to drive the 3-8 line decoder based on the monotype complementary gate, propagation delay can be declined and redundant current can be reduced.3)The current scheme of Manchester encoding has the disadvantage of requiring triple stages ring oscillator and monotype XOR gate for frequence doubling. To solve the problem, a Manchester encoding circuit driven by bi-phase clock is proposed and it is based on the 6 NAND gates of the D Flip-Flop. The improved circuit demands to be driven with a clock and its invert signal. The power delay product is reduced with the new scheme.The simulation result demonstrates that, the power of 5-stages ring oscillator which improved with Re-Pull-Down transistor is reduced by 30.8% compared to the Pseudo-CMOS scheme. The power of the shift-chain drive circuit which improved with Re-Pull-Down transistor scheme is reduced by 15.97% compared to the Pseudo-CMOS scheme. The power of counter + complementary gate ROM reading scheme is reduced by 29.62% compared to the shift-chain scheme. The power of bi-phase Manchester encoding is reduced by 49.69% compared to the XOR gate scheme. After optimized with Re-Pull-Down transistor scheme and counter + complementary gate ROM reading scheme, the power of decoder is reduced by 48.86%.