Research And Design Of High Speed SAR ADC

As the bridge of analog signal and digital signal, ADC (Analog to Digital Converters) is widely used in the field of communications and biomedicine. Compared with other structures of ADC, SAR ADC (Successive Approximation Register ADC) has the features of low power consumption and simple structure. High-speed, low-power SAR ADC has been widely used in wireless sensor networks, multimedia mobile terminals, portable battery-powered instruments and other fields. Thus the research of high speed and low power consumption SAR ADC which has broad application prospects is of great significance.Based on the requirements of high-speed wireless sensor networks, this paper needs to design the ADC with low-power and medium-speed. SAR ADC has the feature of low power consumption, moderate conversion speed and accuracy, so SAR ADC is the best choice to meet the requirements of high-speed wireless sensor networks. This paper researches and designs the unit circuits which can increase the conversion speed, improve the accuracy and reduce the power consumption of SAR ADC. In order to increase the sampling accuracy of SAR ADC, bootstrapped switch is used to realize the sampling and hold circuit; Non-binary capacitor array is used to realize the ADC circuit, this method can reduce DAC setting time and increase the conversion speed of ADC; Dynamic comparator is used to reduce SAR ADC’s static power consumption; Using improved latch and asynchronous timing, SAR control circuit can reduce delay of circuit.SAR ADC is implemented in 1.8V TSMC 0.18μm CMOS process. The area of layout is 1.21mm2. The simulation results show that:when sampling speed is 50MS/s, the effective number of bits is 9.253bit, signal to noise and distortion ratio is 57.46dB, spurious free dynamic range is 64.54dB, when sampling speed is 70MS/s, the effective number of bits is 9.049bit, signal to noise and distortion ratio is 56.24dB, spurious free dynamic range is 67.41dB.The power consumption is 6.2 mW. Simulation results show that this design meets the system design specifications.The ADC is tested at 50MS/s. The ADC can achieve the maximum ENOB of 6.694bit.