Design Of EBPSK Modulation Circuits Based On CMOS Technology

Nowadays, as the spectrum resource is as precious as gold, improving spectrum utilization has become a new breakthrough of ICT development, as a novel communication technology,UNB can greatly improve the spectrum utilization. With the theoretical research of UNB communication technology becoming more in-depth, practical use of it has gradually put on the agenda.The thesis designed an EBPSK modulation chip using TSMC 0.18 μm CMOS technology. The carrier frequency of the modulator range from 200 MHz-2.4 GHz, and can be freely selected in three special modulation modes(reverse modulation mode, MCM modulation mode and narrow pulse modulation mode).The amplitude of the output modulation signal must greater than 300 mV at 50 Ω load.The overall circuit design is divided into three modules, namely, single-turn differential module, switching modulation circuit module and output amplify buffer circuit module. Due to the wide frequency range and large amplitude of the carrier signal, the source negative feedback is specially applied to the single-ended-to-differential conversion circuit. To guarantee the accuracy of switching on and off, a compensation capacitor is additionally used to reduce the mismatch of two output signals. In the switching modulation circuit module, we use the double balanced MOS switching modulation circuit, which can effectively suppress the leakage from the input terminal to the output terminal and the switch control terminal to output terminal, so that the output waveform is more pure. In order to ensure the distorted of output modulation signal, shunt peaking technology is used to improve the bandwidth of the output buffer in this paper. Three stage common source amplifier circuit is used, the amplitude of the output signal at 50 Ω load is much larger than 300 mV.The has been tested through on-wafer and on-board measurement, and the results show that the output modulation waveform achieve the modulation function in 200 MHz-2.4 GHz frequency range. Including the output buffer circuit, the total power consumption of the chip is 30mA ×1.8 V, and the whole chip area is 510 μm ×740μm.