Research On Multi-Core Systems Storage Structure Optimization

In a Multi-Processors System-on-Chip (MPSoC), data exchange frequently between on-chip processors and off-chip shared memory. Network-on-chip (NoC) technology provides the conditions for parallel computing and memory access of on-chip processors. Efficient storage structure supporting multiple parallel memory access is needed urgently in MPSoC. The hierarchical storage system is used in the target multi-core system to partially alleviate the gap between calculation and memory access on chip. This paper combines parallel memory access technology and data prefetching technique to optimize the storage structure of the target system. This paper refers to the time slice circular scheduling algorithm and utilizes the bandwidth distinction between both sides of the memory interface to achieve time-shared exclusive operation on SDRAM side and parallel operations on user side. With above studies, this paper designs and implements a kind of random distribution parallel Multi-Access Memory Interface (RMAMI),and utilizes on-chip memory to complete data pre-read operation to make full use of the bandwidth of memory, play the parallelism of NoC and improve the performance of the target system.The main work is as follows:1. This paper analyzes the principles of RMAMI and presents the design scheme of RMAMI. It discusses the selection of the working mechanisms, such as the mechanisms of arbitration, time slice switching, data channels randomly assigned mechanism, the data prefetching mechanism based on the process and so on.2. This paper designs the RMAMI hardware prototype according to the design scheme which supports that the number of read and write channels are assigned according to need and data ports are assigned according to optimal allotment. The RMAMI design uses on-chip memory as data buffer and takes the idle data channels to complete data prefetching, which can alleviate the data interrupter problem and further improve the bandwidth utilization rate of the external memory.3. This paper integrates the RMAMI design into the target system to replace the MAMI interface. By mapping tasks with different ratio between calculation and memory access, this paper discusses the influence of Data Transmission Parallelism (DTP) and performance of system tasks brought by the RMAMI design. Compared with the original memory interface MAMI, the experimental results show that the average performance of RMAMI improves 21.1% for tasks of computation time similar to memory access time,3.0% for tasks of memory access time smaller than computation time, and 9.7% for tasks of memory accessing matrix transpose task. Above all, the designed interface RMAMI supporting data prefetching can effectively improve the parallelism of data transmission, improve the system efficiency, and fully achieve the expected design goals.