Fault-tolerant Technology And Thermal Optimization Design Based On TSV In 3D NoC

Chip yield and heat dissipation are hot topics in 3D NoC design, and how to design the fault-tolerant scheme for TSVs in 3D NoC becomes a key to increase the chip yield. However, most of existing fault-tolerant algorithms usually adopt local redundancy mechanism, which can’t achieve very high yield and greatly waste unused redundancy resources. Furthermore, they usually only support fault tolerance without any other function such as heat dissipation. In this thesis, we focus on global redundancy mechanism within groups based on functional subdivision to resolve the problem of chip yield and heat dissipation in 3D NoC. The main work is as follows:1. A fault-tolerant circuit based on all-shared redundancy within a group is designed. In order to resolve the problem of the limit of chip yield and the sharing degree of redundancy, these vertical links are divided into several groups, and redundant TSVs are distributed to those groups. Then they can take the place of any faulted vertical link in the group to transfer signals, so as to realize this fault-tolerant mechanism. Yield analysis shows that the traditional fault-tolerant schemes are unable to break through 99%; the new global redundancy method proposed in this thesis, regardless of the TSVs’amount, can achieve 99.999999% chip yield.2. A redundancy optimization strategy based on functional subdivision is proposed. This strategy first divide the TSVs into specially appointed groups, according to the features and importance of the signals. The different fault-tolerant schemes and redundancy rates are implemented according to the importance of the groups to optimize the number of redundant TSVs and as far as possible to reduce fault-tolerant cost. The experimental analysis shows that, compared with old schemes, fault-tolerant scheme based on functional subdivision can optimize about 20% fault-tolerant costs.3. A fault-tolerant scheme combined with thermal optimization is designed. Combining thermal optimization with fault tolerance, the scheme makes signals detour to unused redundant TSVs in the group in turn to reduce the traffic of TSV channels on the premise of finishing fault-tolerant part, so as to balance the temperature on these vertical links. The experimental results show that the greater the number of redundancy TSVs, the better the thermal optimization.