The Software Implemented Fault Tolerance Study Based On COTS DSP

The high-performance digital signal processor (DSP) has been widely used in electronicsystems of the spacecraft. However, due to cosmic ray irradiation-induced single event effects,the reliability of DSP systems constitutes a significant problem. The development of radiationhardened DSP is insufficient, and has been one of restrictions on the high performance spacecomputers. Therefore, effective fault-tolerant techniques must be equipped to improve thesystem reliability. Compared to radiation hardened DSPs, COTS DSPs have very highperformance, lower price and lower power dissipations, size and weight. Based on the COTSDSP, our research applies software fault-tolerance technology to solve the reliability problems ofCOTS DSPs. The incorporation of software fault-tolerance technique and COTS DSPs becomesan important solution to building the high performance onboard computer, which is veryimportant to the independent development of our space cause.Based on the existed software fault-tolerance technology, this paper makes progress in thefault-tolerance technology on DSP architecture. They are illustrated as follows:1. We put forward a software fault tolerant algorithm for DSP architecture based on linearassembly language. Firstly, the effects of the soft errors on function unit and parallelexecution character of C6000series DSP were analyzed, the error generation rule wasobtained. Based on the error generation rule, we proposed a Software Error Detectionbased on Linear Assembly Language technique (SEDLA). The algorithm incorporatedcontrol flow checking and data flow checking together, which made the fault toleranctDSP program have the ability of checking software errors in registers and instructionstorage spaces.2. We put forward a performance optimization technology based on the fault tolerantalgorithm. We firstly made an analysis on the process routing of SEDLA algorithmbased on the redundant check instructions between control flow checking and data flowchecking. The optimization algorithm can reduce performance overhead afteroptimization being committed in processes at the cost of limited fault delays, at themeanwhile the fault discover rate is not degraded. Secondly, we analyse the programexecute clock cycles before and after software hardening. Then we make optimizationson the hardened loop body according to the reason of disqualified loop. We put forwardDSP loop optimization algorithm, which greatly reduces the execution cycles ofhardened programs with a limited fault processing delay and similar error checking rate.3. We designed and implemented a transform tool, which translated an original programinto a fault tolerant one on the linear assembly language level. And then a fault injectiontool was implemented, which enabled statically data flow fault injection and control flowinjection simultaneity. Fault injection experiments were performed to demonstrate theeffectiveness of our fault tolerant algorithm.