The Research Into Response Characteristic And Model Of 550V High-Voltage SOI-LIGBT Under ESD Stress

Silicon on insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is widely used as output device in power integrated circuit, by virtue of its large current density, fast switch speed and easy integration. In order to reduce chip size further, output terminal is not lead in extra Electro-Static Discharge (ESD) protection device. As a result, this requires that the SOI-LIGBT needs to possess ESD self-protection ability. The premature failure of the SOI-LIGBT under ESD stress becomes a bottleneck which restricts the further development of power integrated circuits. Thus, it is urged to investigate the response characteristic and the model of SOI-LIGBT under ESD stress.Based on the 550V SOI process platform, the ESD response characteristic of gate-floating high-voltage SOI-LIGBT is researched in this thesis. The response mechanism including forward blocking region, voltage snapback region, voltage holding region and secondary breakdown region is demonstrated. In addition, the influence of different structures and process parameters including the depth of SOI, the thickness of BOX, the dose of Pbody and so on; the influence of different anti-latch-up structures including cathode with high concentration Pwell, cathode with Psink well and cathode with N+/P+ section structure; the influence of different gate voltages for ESD respond characteristic are investigated in this thesis. The change of these parameters can result in the change of trigger voltage, holding voltage and secondary breakdown current under the ESD stress. The intrinsic physical mechanism is also analyzed deeply by using the technology computer aided design (TCAD) simulation tools. This work can provide the theoretical guidance for the ESD design of SOI-LIGBT.In consideration of the device’s physical mechanism, the whole ESD response model of 550V high voltage SOI-LIGBT is established, including four stages in the ESD response process. Test result shows that the relative error is under 15%. This model is able to predict the important parameters of SOI-LIGBT such as trigger voltage, holding voltage and secondary breakdown current under ESD stress. The model has a positive role in promoting the design of the device.