Equalization Algorithm Design And Implementation For High Data Rate Demodulation

As the modern communication system becomes more complicated in signal transmission, data receiver is facing the huge challenges such as the complexity of demodulation, system processing bandwidth etc. High Data-rate Receiver(HDR), as an essential analyzer wideband communication signal, has a key role in testing of digital communication technology. This dissertation conducts a research on signal equalization technology and its implementation in FPGA hardware, expecting to break through the bottleneck of high-rate data process in HDR, for instance, group delay compensation and multipath adaptive blind equalization.Firstly, the dissertation analyzes the specifications of HDR, then proposes a parallel architecture which can achieve satellite communication signal as high as 400 Msps with low hardware cost by frequency domain signal processing. Secondly, based on the spectrum characteristic of periodic rectangular pulse signal the dissertation proposes a kernel scheme of group delay measurement with single channel. Next, a new algorithm which is based on the principle of all-pass filter to compensate the measured group delay comes up. A high efficient parallel implementation method of the all-pass equalization filter is also developed by comparing the parallel structure of IIR and FIR filter. Moreover, the study develops an iterated short convolution based, effective pipelined implementation structure of adaptive CMA algorithm by introducing look-ahead computation and relaxed look-ahead transformation. The design of algorithm architecture in FPGA is also conducted in detail.Finally, the design has been verified on a HDR hardware platform. The results of group delay measurement and compensation are consisted with vector net analyzer(VNA). The equalization output of HDR hardware platform show that the algorithms are implemented successfully in parallel architecture proposed.