Key Modules And System Desigc Of Neuromophic Chip

In recent years, with the rapid development of deep learning algorithms, large-scale image processing and iterative calculations put a new challenge for hardware. Traditional computers are based on the "von Neumann architecture" design, that is, data calculated back and forth between the processor and memory. This architecture is suitable for digital operation and program execution, but is not suitable for processing images and voice signals. However, the human brain is easy to process visual and auditory signals synchronously. By studying the operating principle of human brain, the academic proposed a neuromorphic chip unlike traditional architecture, which has a significant advantage of dealing with image and sound signals. Therefore, this thesis proposes a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network.This article first introduces the principle and the corresponding circuit models of biological neural networks, theoretically proves the feasibility of neural network circuit design, and defines the internal structure of the chip according to the requirements of application and the limitations of circuits. The chip is divided into four modules, neuron circuit array, synapse circuit array, SRAM (Static Random Access Memory) memory arrays and AER (Address Event Representation) communication circuit. Among them, neuron circuit array and synapse circuit array have temporal dynamics of biological neurons and synapses with spike-frequency adaptation and programmable weight values. What’s more, changing the connection of synapses and neuron circuits can achieve a variety of applications. Using this representation it is able to interface the device to a microprocessor and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module.The chip which fabricated by smic 180nm CMOS technology comprises a total of 32×32 SRAM cells,2×32 synapse circuits and 32×1 silicon neurons. The simulation results show that the chip’s output is same as the algorithm program’s, which indicates the design of the chip in line with expected requirements.