Implementation And Optimization Of Embedded Stereo Vision Subsystem

"Virtual reality" and "augmented reality" has evolved and spread along with the development of wearable devices. Various image processing algorithms are used widely in a lot of chips that based on different architectures and different operating systems.Currently, there is a kind of embedded high-performance processor with multiple cores, which is based on the SPARC architecture. Now it is used in parallel data processing task more and more frequently. The processor includes many computing units, shares cache and memory with each other. And it has an efficient instauction pipeline and independent vector computing units, so the processor can handle complex image processing tasks with these expediency.In this paper, I focused on the algorithm implementation and performance optimization based on the box-matching stereo vision algorithm and the semi-global matching stereo vision algorithm.At the beginning, the paper introduces the research of the algorithm, the Vx3-platform device, the puepose of this research, the significance of the research and the main results of the research. And then I discourse the feasibility of the implementation for the algorithm on the Vx3 hardware.And then, to meet the goal and the feasibility of this subject, I made requirement analysis for the project. The specific content is: the objective of the algorithm, the functional requirements, the performance requirements, and the hardware and software requirements.According to the requirement analysis and the characteristics of the algorithm and Vx3 platform, I discourse the key point of the project which may be occured in the process of the implementation of the program design, then I give out some ideas and resolutions, includes: memory usage, data computation accuracy, static buffer, cache consistence, vector, co-processor symbol consistency. Then the algorithm structure is re-designed, includes: algorithm data flow re-design, re-schedule for the the pipeline, memory usage re-design, etc...According to the design scheme, the code is written and debugged for meeting the functional requirements. And I did the optimization for the code including the instruction pipeline scheduling, DMA using, vectorizing, code branch cutting, handwriting assembly code, so that the full performance of the embedded device system can be preformed.Finally, the code is tested before and after optimization, and the optimization results are given, which can provide a way to porting the image processing algorithm to the Vx3 device efficiently.