Design Of Ka-Band Automatic Gain Control Circuit

Due to the influence of external factors, the unstable received signal has a wide dynamic range in a wireless communication system. Therefore a circuit is needed to maintain stability of the received signal. The Automatic Gain Control Circuit (AGC) keeps the received signal stable for the correct demodulation of the signal.The paper introduces the knowledge of radio frequency circuits firstly, including the characteristics of RF device and the analysis of wideband circuits. Each part of the AGC system is improved based on the relevant theoretical knowledge of wideband circuits.The AGC system is further researched based on the relevant theoretical analysis about the basic structures and the performance indicators of the automatic gain control circuit in the feedback control system. Automatic gain control circuit is mainly composed of variable gain amplifier (VGA), peak detection circuit, comparator, control signal generating circuit, etc. In the process of design, we should consider the performance indicators of the automatic gain control circuit, such as dynamic range, response time, etc. The circuits are designed in SMIC 0.18μm RF CMOS process. Supply voltage is 1.8V. Working frequency is between 27.5GHz and 31.3GHz. The center frequency is 29.4GHz. The input range of the automatic gain control circuit is between -20dB～20dB. Based on the theoretical analysis of the circuit, every part of the optimal circuit structure is designed and simulated to satisfy the basic requirements of the AGC system. The Chebyshev band-pass filter is used for filtering the input signal. The Gilbert structure with extended bandwidth technology is selected to design controllable gain amplifier. The current mirror structure composed of MOS tubes is used for the peak detection circuit. The control voltage generating circuit is designed based on the exponential relationship between the voltage and the current of the transistors.The simulation tool is Cadence SpectreRF in Cadence environment. The layout of circuits is extracted parasitic parameters for the back-end simulation. Although the post simulation result is different from the pre simulation, the deviation of the stable output voltage is about lOmV. The overall layout area is around 1.15mm.