Design And Implement Of SRIO Logic And Transport Layer Unit On DSP-X

DSP-X is a high performance Digital Signal Processor with fixing-point and floating-point founction on it, which is independently developed by ourl University. DSP-X integrate two Serial Rapid IO IP cores supporting Rapid IO interconnect specification of version 2.1 and being used to support the communication within chip or chip-to-chip. RapidIO interconnect specification of version 2.1 includes three parts: logical layer, transport layer and physical layer. Logical layer defines all the protocol and the format of packet; transport layer difines the route of RapidIO packet; physical layer difines the link control mechanism. This paper depends on the study of Rapid IO interconnect specification of version 2.1 and designs the Logic and Transport Unit of Serial RapidIO(SRIO).The Logic and Transport Unit implements logical and transport layer protocols of Rapid IO interconnect specification of version 2.1, which is segmented into OB outbound link, IB inbound link and Cofigurable registers. In the IB inbound link, it’s used C ycle-forward mechanism to segmet the RapidIO packet, and implement error management of logical layer and transport layer, and supporting up to eight packets stored in buffer temporarily, and transform data from IB interface to SRIO by using handshake mechanism. And in the OB outbound link, it’s implementing the data information converted to Rapid IO packet, and supporting up to eight packets stored in buffer temporarily, and doing the reordering basing on priority levels among the packets wthich is stores in the buffer, and assigning a transaction ID(TID) to the winner packet. It is also used C ycle- forward mechanism to assemble Rapid IO packets and cut through forward the Rapid IO packets. In addition, Configurable register provides transaction operation enabled, including NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC, MANINTENANCE and DOORBELL. It also note s the error checked in logical layer and transport layer.This paper also does the simulation verification of the design in the administrative levels and describing and comparing the results. Based on all of the result, the Logic and Transport layer Unit we designs can support RapidIO transfers, eight packets stored temporarily in the link and packets reordering, also support 1x/2x/4x mode and the speed of 1.25 Gbps, 2.5 Gbps, 3.125 Gbps and 5.0Gbps, which is satisfing the design requirement of DSP-X.