A Front Algorithm Research On A High Frequencyband Radar Signal Processor

Digital receiver for radar signal processing system core components, according to radar compact, lighter development needs, accompanied by the development of digital signal processing hardware technology, the use of single-chip core manner is becoming mainstream. This paper elaborates on the day of wave OTH radar digital receiver front-end algorithm based on the principles of flow and Kintex-7 series FPGA chip implementation process.Traditional radar signal processor because the hardware level of development restrictions, often requiring multiple data processing center, then cascade parallel computing, in synchronization, fault tolerance system of indicators is not optimistic. The system is certified by the theoretical analysis, using a single FPGA chip to complete the multi-channel digital down-conversion, low-pass filtering and pulse compression technology, greatly simplifying the hardware structure, and enhance the system stability.The article first analyzes the origin and significance of the subject, about the development status OTHR and study abroad, also analyzed the research status commonly used in radar signal processing digital down conversion and pulse compression technology.The article went on to owe at the beginning of the sampling theorem detailed analysis of the theoretical knowledge about the digital down-conversion, respectively, were analyzed in the DDC decimation filter, a compensation filter, plastic filter algorithm principle and algorithm simulation, through all levels of the cascade form 75 M success of the carrier frequency are swept chirp signal frequency to zero frequency, and has a good stop-band attenuation, and then introduced to the slope of the pulse compression processing theory, and on this basis to make a return signal The slope of the LO signal to the simulation results.In the simulation model, based on the third chapter focuses on the system receiver FPGA implementation. Design AD collect data from the beginning, through the logical design module and the official IP core in order to achieve the filter module and pulse processing module, the filter module for a more detailed analysis of parameters, in order to guarantee stable data transmission, using the AXI-4 way bus IP core selection. Meanwhile, in order to ensure the stability of system metrics, system synchronization requirements for additional design, with trigger module.The fourth chapter describes the various stages of the validation process of the receiver, combined with ISE authentication method using MATLAB simulation and online logic analyzer(Chipscope) coordination inserted in engineering analysis program, collected by the analyzer to the computer further measurement analysis direct analysis of the problem, to speed up the overall progress in achieving.