Research And Implementation Of LTE Downlink Synchronization Algorithm

LTE system gets rapid development in recent years because of its higher data rates and spectral efficiency, lower latency and configurable bandwidth. And synchronization technology is one of the keys of LTE system. However, current research on synchronization technology mostly only contains a part of synchronization process, and only a few of the studies covering the entire LTE system synchronization process. In addition, most studies are about algorithm and only a few are about the FPGA hardware implementation.This paper studies the synchronization algorithms of LTE system downlink physical layer. Through the simulation and performance analysis of these algorithms, an improved SC algorithm based on the accumulation of correlation value and a synchronization algorithm program under the EPA5 channel environment are proposed. Combined algorithm performance and implementation complexity, the hardware design of synchronization is put forward, and the FPGA implementation and verification are completed.At first, the development of mobile communications and the overview of the LTE system are introduced. Then the significance and research status of the synchronization technology in LTE system are analyzed. And the introductions of some basic principles of the LTE system downlink physical layer are followed by.Then the synchronization algorithms of LTE system based on multipath fading channel models are studied, including PSS timing synchronization, CP type detection, frequency offset estimation and SSS detection. Also, the simulations of synchronization algorithms are completed respectively in EPA/EVA/ETU channel models based on the Matlab simulation platform of LTE downlink physical layer. And according to the analysis and comparison of the performance of these algorithms, a synchronization algorithm program based on the EPA5 channel environment is proposed and its performance analysis is completed. Also, an improved SC algorithm based on the accumulation of the correlation value is put forward, which effectively reduces the phenomenon of peak platform and the detection error probability is reduced by about 50% at high SNR.Finally, considering the performance and implementation complexity, the hardware implementation synchronization plan is presented and during the process of the structural design some skills are used to reduce the amount of calculation or delay. Then, synchronization module is implemented on XC7K325 T and its functional correctness is verified by comparing the simulation results of Modelsim and Matlab. This module can meet the LTE downlink peak rates of 100 Mbps. The synthesis report indicates that the resource consumption is within 60% and the maximum frequency is 304.062 MHz. At last, the board-level verification of synchronization module based on MSUC platform is completed and the results indicate that the implementation of synchronization module meets the needs of the project.