The Design And Implement Ation Of The Digital Cancellation System Based On DSP And FPGA

With the development of science and technology as well as the needs of people living, the frequency modulated continuous wave(FMCW) with asingleantennais used widely. The attendant problem is that the transmitter signal of FMCW radar has a more serious leak to the receive path, it influences and restricts the further development of the radar.The research purpose of the thesis is that to conduct research on the outstanding issues of FMCW radar and make the leak of transmitter reduced to a lower level. The research content of this thesis has the theoretical basis and practical basis and it has acertain significance and application value. By solving this problem, this can increase the effective distance of the radar, thereby further expanding its applications and ranges.The main work of this thesis is to develop a hardware platform design of digital systems and complete the acquisition and conversion of the IF signal, signal transmission, control, and FPGA simulationan dimplementation of cancellation-related preprocess singal gorithmon the digital system hardware platform. Thus, according to the amplitude and phase information of the current leakage signal, to make real-time calculation and output the feedback control amount to control the RF cancellation section, to achieve inhibition of transmitter leakage signal.First, this thesis introduces the research purpose, significance and domestic research situation of this subject, compare the advantages and disadvantages of several common design, summarize and draw the design scheme used in this thesis. The design scheme is adding digital control system in the basis of the traditional RF cancellation, thus achieving the accurate and adaptive control for RF cancellation module.Secondly, according to the technical indicators of the system requirement, combined with the considerations of the practical factors, planning and division the functions of the various parts of the digital hardware platform. According to the digital system design scheme, to design a set of digital hardware platform. The hardware platform uses the CPCI bus architecture and DSP+FPGA co-processing mode to build complete with AD, DA, op amps and other peripheral modules together.Furthermore, this thesis describes the process of signal processing algorithms used in the system.And other aspects of the algorithm FPGA, it describes the principle and structure of the energy detection algorithm and digital down conversion algorithm and other preprocessing algorithm in FPGA. To make a series of simulation used with MATLAB, ISE and other related software and realize the above algorithm based FPGA.Finally, to implement the hardware platform based on the high-speed PCB design guidelines and make the board-level testing and validation for each hardware system modules and algorithms, to make the joint testing combined with the RF module, thus completing the overall system functional verification. The results show that the signal leakage power decrease after adding a digital system. To test the whole system with binding circulator isolation in the range of 300 MHz bandwidth which the center frequency is 9.41 GHz, almost all can achieve to cancellate more than 70 dB. To swep the system in 30 MHz bandwidth which the range is 9.54 GHz to 9.57 GHz, the average cancellation is 63 dB, the center frequency can reach 68 dB, so the results basically meet the system design requirements.