The FPGA Design & Verification Of TCP Protocol

Since 21’st century,we human society has been into the age of digitization and informatization.The development of information technology has been an important factor that drives the way of people’s life to change.The present of Internet of things,cloud computing and big data has been an explicit sign that information technology has come into a new stage.Nowadays,an important support of information technology is the high speed Internet.To realize the high speed Internet,we must overcome the shortcoming such as the long delay and low throughput. The hardwired of TCP/IP protocol is an effective solution to solve the two problems.To achieve the science technology,many countries spend mounts of money and lots of researchers on it.So,the paper studies the hardwired of TCP which is the key procedure in hardwired of TCP/IP.The RFC793 protocol is taken as the criterion in this paper.After looking up mounts of reference and internet resource,the TCP offloading engine based on FPGA is designed.Three parts which are the TCP transmitting and processing module,the timer or counter,the TCP receiving and processing module consist of the design.The TCP transmitting and processing module is taken as the core of this design.Generating the checksum and control signal,packing the data,buffering the datagraph,running of the state machine,traffic controller,regulation of timer threshold is realized by it.Recording the time is the main function of the timer.Unpacking the received datagraph,checking the datagraph and buffering the received data is implemented by the receiving and processing module.The ISE 14.7 is used as the software platform in this design.The Verilog HDL is the programming language in this design.The simulation tool is the Isimulator which is a part of ISE 14.7.Sub-module and whole is simulated in this section.After simulation,the TCP module and UART module are combined into an communication entity with some interface..Then,synthesizing,placing and routing is conducted.In the end,the bit files generated with different port number are downloaded into two FPGA boards NEXYS2.During verification,the state of LED and Nixie light on board improves the correction of this design.At the same time,the Logic Analyzer is used to watch some internal signal of Start_signal_generator module.The result accords with the logic timing of this module.At the end of this paper,the delay of processing datagraph in this design is analyzed in detail.The analysis shows that the maximum processing time is 26.36 us and 26.31 us When transmitting datagraph and receiving datagraph.Meanwhile,the minimum processing time is 192.5ns and 136.3ns.After looking up some reference,the traditional TCP processing time is milliseconds at least.In the end,the paper draw the conclusion that the TCP offloading engine has the less datagraph processing delay.