Research On Key Techniques Of Printing Cable Character Optical Recognition Algorithm Based On FPGA

As the nation’s core infrastructure supporting industries, cable industry gained rapid development, better management is needed for cable automated production and testing. Simultaneously, with the development of industrial machine vision in the field of automation, as the key technology of unmanned automated production, it is very important to research optical character recognition to recognize the printing charater.An optical character recognition system for real-time detection was discussed in this dissertation. The core research was to design a production line recognition algorithm, which can meet the requirements of real-time detection, and can overcome a variety of factors that affect the correct rate of recognition, such as lattice leak spray, adhesion, breaking character and large noise. Then, design and test the algorithm on FPGA was discussed.Two study methods were discussed in this dissertation.The first one was to complete the design and test of dot character recognition algorithm by theoretical simulation. Another one was to complete the algorithm implementation on FPGA by digital circuit.Theoretical simulations complete the main algorithm simulation using MATLAB, including image filtering, binarization, morphological work of dot matrix character, segmentation, feature extraction, character classifier. Due to the particularity of dot matrix characters to be detected, corresponding optimizations were designed in two areas including character feature extraction and character classifier. Considered the 5 * 5 dot matrix structure of the characters to be detected, three different feature vectors were extracted. The first one was traditional direct template matching using difference and coincidence, then 5 * 5 grid statistics, and the last one combine projection histogram and grid statistics. The characteristics of fixed-point and float-point arithmetic on FPGA were taken into account, maximize the use of FPGA parallel computing hardware as well as its pipeline design feature. Parallel classifiers were designed for calculating character match degree under different feature vector groups. At last, voting circuit was programmed to decide the final recognition result.DSP arithmetic circuits are the core units of the algorithms realized by FPGA, such as fixed-point adder, subtractor, multiplier, floating point multiplication, division, and square root. Highly parallel, pipelined calculation circuits were constructed on FPGA to complete the identification algorithms. At last, the performance of the circuits was computed by static timing analysis, then the computation time was evaluated to analysis whether the system can meet the requirements.The experiment result and theoretical analysis show that the design can fully meet the speed and recognition rate requirements. The algorithms implemented on FPGA can complete the work by about 3 ms, which was achieved by digital circuits without using DSPs or on-chip SOC CPU.