Research On Forward And Reverse Conversion Algorithm Based On RNS

Over the past four decades, semiconductor technology has been developed rapidly,and the device feature size continues to decrease, which makes the integration of chips continue to rise. Higher and higher integration not only makes it difficult to manufacture chips, but also makes the contradictions among area, delay and power consumption on chips more prominently. So Very Large Scale Integration(VLSI)technology faces enormous challenges. It is found by relevant researchers that VLSI systems with Residue Number System(RNS) can effectively balance the relationship among area, delay and power consumption to achieve low power consumption,high-speed VLSI design. Therefore RNS is paid a lot of attention and researched deeply.This dissertation centres on the forward and reverse conversion issue in RNS to do deep research. Improved forward and reverse conversion algorithms and specific VLSI implementations are introduced. The improved algorithms not only have good versatility, but also effectively reduce the implementation complexity, which makes a positive effect on better application to VLSI with RNS.The conversion from binary number system to RNS which is often called forward conversion is inherently modular arithmetic. Conventional forward conversion is implemented based on Look-up Table(LUT), Processing Elements(PE),combinational logic circuits and et al. The third chapter improves the forward conversion algorithm with the congruence theory based on the moduli set {2 }n?k.Improved algorithm converts modular arithmetic of large inputs into modular addition of several small product items. All the product items are calculated parallelly and individually, which reduces the conversion delay and the complexity of VLSI implementation.The conversion from RNS to binary number system which is often called reverse conversion is implemented conventionally based on the theories of Chinese Remainder Theorem(CRT) and Mixed Radix Conversion(MRC). The third chapter improves the CRT with the congruence theory to convert the complex modular arithmetic of M( M is called dynamic range) into multiply-add operations with?X,*? and M. And through theoretical derivation, there exists simple corresponding relationship between?X and*? under certain conditions, which can significantly reduce the complexity of VLSI implementation.Above improved forward and reverse conversion algorithms are assessed in the fourth chapter. At first, the proposed algorithms and contrast algorithms are separately modeled with hardware description language Verilog HDL. And then all designs are synthesized with Synopsys synthesis tool Design Compiler based on SMIC 130 nm standard library, generating the reports about area, delay and power consumption to evaluate algorithms. Synthesized results show that the improved forward conversion algorithm can achieve "Area×Delay×Power Consumption"(ADP) complexity savings of 49.8% and 47.9%, respectively when compared with Premkumar algorithm, the partition compression algorithm and the improved reverse conversion algorithm can achieve ADP complexity savings of 84.4%, 79.6% and 48.9%, respectively when compared with CRT-II, MRC-II and the error correction algorithm. In a word, the proposed algorithms are better than the other algorithms for comparison and are more suitable for VLSI implementation.In the fifth chapter, the improved algorithms are applied to the design of FIR digital filter, and achieve good results. Validation on FPGA hardware platform indicates that RNS-based FIR digital filter not only consumes less resource, but also improves the characteristics of timing and power consumption at some extent when compared with the traditional design. In other words, RNS-based FIR digital filter achieves better performance. And this also incarnates the significance of RNS application in signal processing systems.