ADC Design Based On Low Cost Process

The line width decreases as the development of integrated circuits industry, there are two trends that the new node process cost is increasing and chip design combines with process closely. Based on TUD DIMES low cost process line, this paper has designed an ADC system. Being the first time for the process to design large scale IC, the following work is done and included in the contents.Based on the deep understanding of each process step, the author does process simulation and gets the process parameters such as dopant profile, junction depth and surface dopant concentration. Process simulation and device simulation is conducted on SN resistor. The accuracy and reference value is confirmed by the comparison between simulation and measured results. The transfer character curve of NMOS under different substrate bias condition is also simulated.The BSIM 3v3 model for NMOS and PMOS is modeled by the measured data of different substrate bias condition, different dimensions and different operation region. The SN resistor model including width encroachment effect coefficient, temperature coefficient and voltage coefficient is also extractedThe author creates technology library files for the process under the environment of Cadence ICFB. The design rule comes up after the analysis of process flow. The layout design rule file and LVS rule file are written with a research of the EDA software syntax.At last, the author selects proper SAR ADC architecture based on the characteristic of the DIMES process, conducts the capacitors and resistors mismatch requirement by the DAC block, finishes the design of the ADC system, improve the timing circuits block and comparator block, and conquer the defects of high threshold voltage MOSFETs by clock boost circuits. The system simulation shows the ADC ENOB is 7.8 bit under the sampling rate of 90.9K/S and it can guarantee DNL and INL less than 0.5 LSB. The whole circuit is taped out under this process.