A Study Of The Infrared Image Preprocessing System

Infrared Focal Plane Array technology(IRFPA), which has brought a revolutionary change to infrared detector. With the help of this technology, infrared detector not only gets better performance on sensitivity and signal-to-noise ratio(SNR), but also takes the advantages of simple structure and high integration. This kind of infrared detectors are widely used in the infrared image acquisition. However, due to factors such as craft, material, images obtain from the IRFPA infrared detector would appear some problems. For example, pixel response non-uniform, defect pixel and image edge blur problems and so on. These problems will seriously affect the quality of the image. In order to overcome the problems above, an image preprocessing system is needed.Firstly, the thesis analyses the problems caused by infrared detector defects, and then gives the corresponding algorithms to resolve these problems. For solving the problem of pixel response non-uniform cause by the infrared detector, two-point correction algorithm is given. For handling the problem of defect pixel, a non-linear digital filter based on adjacent pixels is given. In order to overcoming the problem of edge blur, an image enhancement algorithm based on histogram equalization is placed on infrared image preprocessing.Secondly, we give a suitable FPGA system design for infrared image signal preprocessing which is based on the theory of the previous analysis. According to analysis of the hardware requirement, we focus on the implementation of the key modules in hardware system, and discuss about how to work out the design. Because the system design refers to the requirement of supporting multiple module parallel access to external DDR2, the latter part of the thesis discusses about how to satisfy the demand of DDR2 parallelized access. As the result of space limitation of the circuit design, thesis adopts the solution the space should be shared between FPGA configuration data and user data in the same Flash chip. For meeting this requirement, thesis also gives a new way of data combination based on EPCS.Finally, As to the implementation of the hardware system, the thesis gives some simulation results based on Model Sim and some test analysis based on Signal Tab II to verify the function modules such as static parameters load module,DDR2 parallelized access module and infrared image non-uniform correction module.