The Implementation Of Joint Turbo Decoding-network Encoding Scheme With FPGA

Two-Way relay channel can be looked upon as an important component unit of the wireless network. Physical network coding can effectively improve the transmission rate and throughput of the communication system. And as we all know due to the near to Shannon limit performance, Turbo Code has been widely used in many different systems. Using Turbo coding scheme in two-way relay channel can not only improve the throughput of the system but also improve the network efficiency based on reliable transmission. This thesis tells a way that combining Turbo coding scheme with physical layer joint network coding. And implemented this scheme on FPGA(Field-Programmable Gate Array).This thesis tells the basic principles about the model of two-way relay channel. And based on it a way that joint design of Turbo code and physical layer network coding is proposed. This way improved the throughput compared with the traditional way. In this scheme, a method of sum Trellis is involved to decoding the information that the relay received. This method is used to decode the sum information to mode information, and then broadcast this information to the two mobile stations. So it can reduce the time of exchanging data and improve the performance of the system. The simulation result shows that when compared with the scheme used MMSE, the performance of our scheme can be improved by about one order of magnitude when the SNR is 0.6d B, which proves the correction and the advantages of our scheme.It costs lots of memory and computing resources when the scheme be implemented on FPGA. Because of the complexity of the sum Trellis algorithm is high. So it is necessary to reduce the algorithm complexity. After simplifying we get a Max-Log-MAP algorithm which based on sum Trellis. Then this thesis makes a simulation about the parameters that affect the performance and discusses the problem that how to choose the correction factor. Finally we give the detail hardware implementation parameters.This thesis gives the detail scheme of this algorithm implemented on FPGA. And then this thesis describes the framework of the hardware implementation. After the overall framework, the design ideas and functions of each module in the framework are given.Finally, the hardware resource and the disadvantage of our hardware implementation scheme are analyzed.