| With the development of multi-core technology in recent years, an increasing number of cores are integrated in the processor which requires the programmers have to master the Parallel programming technology. Indeed, several parallel development models have being mature, such as the parallel framework based on the idea of Google’s Map Reduce and shared memory architecture implemented on multi-core processor, the inter-core communication interface MCAPI with independent of the language, the processor and OS. Currently, the use of multiple low-frequency core integrated into a processor through Mesh network architecture has reached the advanced level on the processing performance, and Tilera series processor is one of the representatives.First, this paper studies the architecture and the inter-core communication model of Tilera multi-core processor, the biggest characteristic of which is the system architecture and communication model of the two-dimensional i Mesh network. Second, this paper studies two common parallel programming model MCAPI and Phoenix, and implements them on the Tilera multi-core processors. Finally, this papers implements the parallelization of image enhancement algorithm on the Phoenix parallel programming model.In order to verify the efficiency of parallel algorithms on Tilera multi-core processors, this paper tests the efficiency of MCAPI inter-core communication implemented on Tilera TILE-GX36. Meanwhile, by using the standard datasets testing and analyzing the performance of the Phoenix framework, we found the problem existed between the number of core and the execution of the program, and its the main performance bottleneck is from the I/O stress. Finally, this paper tests the low-light image enhancement algorithm implemented in Phoenix and analyzes the performance using different numbers of core and different enter data, and the results verify that Phoenix parallel framework can improve the efficiency of program and easy to implement. |
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