The Design And Implementation Of Security SOC Chip RNG Module

As the increasing national support of the information security industry, Almost every product which interact with the Internet requires security guarantee. As an integral part of security SOC chip, the random number module gets more and more attention, and more stringent requirements on the randomness. Random number generator is the foundation of encryption applications, it can be used to generate an encryption key with the specify security requirement, outer side channel attack, generate initial vector and random padding bits.This paper describes a design of the random number generator module in a security SOC chip, including the true and pseudo random number modules, as well as the relevant functional modules. In the beginning of the design, we perform a extensive research on the common market design methods. After careful analysis, we strictly develop a suitable design scheme which fulfill the security requirements of this chip. All kinds of verification are continuously performed throughout the design process for detecting the design inadequate earlier and timely modifying. We also conducted the slave and master simulation, as well as the finished product test to ensure the correctness of the entire design. After tapeout, we collect the required number of random samples form the sample chip to conduct randomness test. The test results indicate that the design can achieve the required randomness, it is sufficient for the safety requirements on cryptography, and meeting most applications on the market.This design has achieved some innovation:The module applies the design for testability for the self-test of the random number which based on AIS31 standard. The design approves accessible registers for the the data which need test. The designed random number module can pass the self-test and the randomness test specification, the chip has got a strong security guarantee.The module has implemented the cross clock domain design which can effectively improve the generation rate of random number. At the same time, it not only support the faster algorithm clock and the slower algorithm clock, even meet the situation when two clock vary widely meet different users. The design can satisfy the use of different users.The module is based on the design of the bus interface, support for word, half-word and byte access, every functional modules is individually designed. We can configure different clocks, different division ratio, which enhanced the module portability and the flexibility of use.