Research And VLSI Implementation Of Reconstruction Algorithm Based On Compressive Sensing

Compressive Sensing (CS) is the new rising theory in the areas of Signal Processing. This theory states that we can samples the signals with lower rate than the traditional Nyquist theory suggested, and the signals can still be reconstructed accurately when only has little sampling data, if the signals are sparse. Such superior qualities make it has broad application prospects and it has been studied extensively.Signal reconstruction is a very important part of compressive sensing theory, and there are so much research has been done by domestic and foreign scholars. Among these algorithms, they focused on three directions, one is convex optimization algorithm, and one is greedy algorithm, and one is combining algorithm. The greedy algorithm, which has small computational complexity, fast reconstruction speed and can be easy to implement, is more conducive to practical application than the other two algorithms. This paper design and realize a reconstruction algorithm accelerator based on the subspace pursuit algorithm (SP) which has more superior performance than other greedy algorithm through simulation analysis. The subspace pursuit algorithm has been improved and optimized in comprehensive consideration of performance, reconstruction time, practical implementation area and any other factors. In the subspace pursuit algorithm, there are twice least-square operations which makes it harder to imply in hardware. We optimized it for just only one least-square operation to do which not only reducing the computational complexity and implementation area and reconstruction time, but also ensuring the good reconstruction accuracy.For the specific hardware implementation, in order to improve the performance of the circuit, the Alternative Cholesky Decomposition (ACD) algorithm has been used to take the inverse matrix operation and the algorithm has been designed as a systolic array structure. The division which is a hardware implementation complex cell, has been substituted by subtraction and shift, thereby removing the critical path delay and also reducing area. By sharing the multiplication in the ACD module to complete the multiply operation in other modules, the circuit area has been further reduced. The reconstruction algorithm accelerator utilizes a measure vector with 64 elements to reconstruct a digital signal with length 25 and sparsity 8 through Gaussian random distribution matrix. By using SMIC 65nm CMOS technology, the synthesized design area is 2316K Gates and working frequency can achieve 222.2MHz.