Design And Implementation Of Sparse Signal Processing Algorithm Based On Compressive Sampling

Compressive sampling(CS) provides a new signal processing paradigm that samples the signal with lower rate than traditional Nyquist theory suggested, the signal can still be reconstructed with high probability. The bottleneck aroused such as the sample rate increases with the bandwidth, samples are hard to got and the waste of sample resources by sampling first at Nyquist rate then rejecting the redundancy can be solved with the application expansion in the real world. The theory has rather bright future research and application prospect.Signal reconstruction is an important part of compressive sampling theory. Greedy algorithms are effective sparse signal reconstruction algorithms with low computational complexity and fast convergence rate.Among all the efficient greedy algorithms, Subspace pursuit(SP) algorithm provides accurate and stable reconstruction results with proper computational complexity. This paper takes reconstruction algorithm performance, calculation speed and implement area into consideration, then design and implement a signal reconstructor based on SP algorithm. The design optimizes the original algorithm by1) simplifing the initialization step, combining the correlation and residue updating steps together;2) substitute the L2norm by L1norm to perform vector absolute value calculation;3)substitute the least square equation to a Hermite Toeplitz matrix with circular symmetry property and remove the least square operation after generating the optional candidate list are also utilized. Those optimizations don’t affect the critical point appeared in totally reconstruction case obviously,however,the calculation complexity and delay are reduced further.When comes to the hardware implementation,this paper designs a matrix multiplication array with21real multipliers which can directly finishs the2x2matrix multiplication.Then utilizes it to iteratively solve the Least Square equation through Strassen algorithm. Several improvements are got through1)using the looking ahead technology to overcome the long calculation delay of inversion factor appeared in the inversion calculation with adjoint matrix.2) concurrently performing the matrix pre-calculation and residue updating calculation.3) Reused the multipliers array in initialized correlation calculation and residue updating process in each iteration rounds.The reconstructor utilizes a measure vector with30elements to reconstruct a digital signal with length32and sparsity3through Partial Fourier Transform. By using TSMC0.13um CMOS technology, the synthesized design area is188k Gates. The working frequency can achieve277MHz. Compared with the existing referenced results. The design achieves a good balance between reconstruction performance and implementation complexity.