Study On Surface Damage Of Silicon Wafer Polished By Ultrasonic Atomization CMP

With the continuous development of semiconductor industry in present times,monocrystalline silicon has become important fundamental functional materials of semiconductor devices and integrated circuits. Moreover, the requirements for surface quality of silicon wafer become more and more strictly. Chemical mechanical polishing(CMP) is one of the mainstream technology to realize the smooth of wafer surface. However, there are some disadvantages in traditional CMP such as waste of polishing liquid, inconsistent material removal, uneven distribution of abrasive. Based on the above defects, ultrasonic atomization slurry technology was provided to save the consumption of polishing liquid and make further improvement on the surface quality. But it will cause surface damage of silicon wafer and affect performances inevitably due to the process itself. So it is necessary to study the surface damage of hard brittle crystal which is polished by ultrasonic atomization CMP in order to improve the measurement and detection methods based on surface precision and quality requirements.The surface damage forms of silicon wafer which was polished by ultrasonic atomization CMP were detected and analyzed. The surface quality was discussed quantificationally and qualitatively by using SEM, AFM and other instruments. The results show that surface roughness of silicon wafer is under 10 nm and there are no scratch and fragmentation on surface. Then using chemical etch method and micro-raman technology to characterize the microcrack,dislocation and residual stress of sub-surface. The results show that the micro-crack becomes worse when the subsurface depth increases. Besides, the dislocation density in edge area is lower than other areas and there are no serious defects such as dislocation row and low-angle boundary. The dislocation density can be reduced effectively by increasing the atomizer power. In addition, wafer is added residual tensile stress after polished and the stress distributes symmetrically along the diagonal direction. What is more,the residual stress increases from center to edge.Differential etch rate method was adopted to measure the subsurface damage depth of grinding silicon wafer after polished and made a comparison with traditional CMP under same process parameters. The results show that subsurface damage depth of silicon wafer polished by special polishing liquid(0.83μm) is lower than purchased SSP-L polishing liquid(0.99μm). Material removal rate is a bit lower by comparison to traditional CMP, but subsurface damage depth is lower. Then making a research about mechanism of surface damage and the study suggests that damaged layer consists of hydrolysis layer, defect layer and residual stress layer.Establishing orthogonal matrix analysis model to optimize process parameters and thecomprehensive assessment index was based on subsurface damage depth, surface roughness and material removal rate. The analysis suggests that the primary and secondary order of polishing process parameters that affect the comprehensive assessment index is atomizer voltage, polishing pressure and polishing pad speed. The optimal combination of process parameters is atomizer voltage 50 V, polishing pressure 8psi and polishing pad speed 60r/min.In this circumstance, material removal rate is 166.488nm/min, subsurface damage depth is0.83μm and surface roughness is 4.9nm. After that, the effect of process parameters to subsurface damage depth was studied by individual factor experiment. The results show that subsurface damage depth could be reduced by increasing the voltage of atomization. However,both the speed of polishing pad and polishing pressure have a best parameter to get the minimum.