Hybrid Compression Of FPGA Configuration Files Base On Bitmask & Rle Algorithm

As a semi-developed circuit FPGA (Field-Programmable Gate Array) not only solves the shortage of ASIC functional logic flexibility, but also overcoming the original gates of programmable devices very limited number of drawbacks. More and more widely used in telecommunications, high-performance computing. With the continuous improvement of integrated circuit manufacturing process, the rapid growth of the size of the FPGA chip resources. Scale FPGA configuration file also will be rapid expansion, but its configuration is relatively slow rate of technological development, on-chip storage space is very limited direct impact on the FPGA use in many of the requirements of real-time applications is relatively high.The main response is to use PC configuration file compression, and then to reduce the profile size by then configure the circuit on-chip decompression mode, change the configuration to increase the bandwidth of the circuit. Existing studies mostly focused on how to design the compression algorithm is more fully utilize redundant field or use special features to provide better compression ratio (CR= pre-compressed data file size/compressed data file size [1]), reduce configuration file size. The former enables compression algorithms and decompression circuit are very complex, and can not provide a satisfactory real-time, and complex decompression circuit chip will take up a large number of resources. The latter design special parts, a limited range of applications.In this paper, the existing compression and decompression program presents a hybrid Bitmask and RLE compression algorithm based on the former field for similar good compression effect can be improved, which is repeated for successive fields have better compression ratio. In this paper, the ingenious combination of two appeal compression algorithms, to improve compression efficiency, as well as relatively simple Bitmask single RLE compression algorithm does not increase the length of the compression field, providing a better compression ratio. While the configuration circuit design, multi-buffer queue, each cache buffer queue fixed-step way to replace the common single cache queue buffer cache more step of the way. Greatly reducing the decompression circuit complexity, providing a higher operating frequency.The test results show that the hybrid proposed compression algorithm provides a better compression ratio, which greatly reduces the size of the profile, test dozens of commonly used IP core selected as test subjects, compared to four in compression algorithms reduce the minimum compression ratio 11.7% up to 21.6% on average by 15.7%, while its decompression circuit operating frequency can reach 300mhz.