Design Of An FPGA-BASED Underwater Acoustic OFDM Communication System

With the exploration and utilization of ocean, people are paying more and more attention on research and development of the underwater acoustic communication system. How to achieve the reliable information transmission has become an important research subject. Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier parallel transmit technique. And its most remarkable character is the high spectral utilization efficiency as well as the excellent resistibility to multi-path interference. Now OFDM is used in underwater acoustic communication. As FPGA is working parallelly, it is suitable for implementation the OFDM algorithm. So design of an FPGA-based OFDM underwater acoustic communication system has important practical significance.In this thesis, we describe the basic principle of OFDM technology. And a brief introduction to the basic structure of FPGA design is presented. As FPGA is suitable for parallel processing the thesis designs an FPGA-based OFDM underwater acoustic communication system. Works and achivememts are presented as follows.(1) First of all, the basic transmission characteristics of the underwater acoustic channel are introduced. Secondly the basic principle and the main technique of the OFDM technology are introduced. Finally the system’s architecture is proposed according to requirement analysis.(2) The thesis proposes the concrete realization scheme for the OFDM underwater acoustic communication system. The OFDM system is divided into two parts:a transmitter and a receiver, the transmitter is responsible for completing the data modulation, where the bit stream sent by the host computer into OFDM symbols. The receiver has to demodulate the received OFDM symbols into bit stream. The all modules of FPGA are designed:The transmitter contains Data preprocessing module, Data mapping module, pilot-inserting module, an IFFT and cyclic prefix inserting module, and a digital UP-Convert module. The receiver contains a digital down converter module, a frame synchronization module, a time reversal processing module, and a channel estimation module.(3) The Verilog language is used to describe the structure, a logic synthesis and hardware test are implemented on Xilinx FPGA.