Implementation Of IDEA Encryption Algorithm Based On FPGA

With the rapid development of communications and computer technology, the storage and transmission of information has undergone tremendous changes. More and more information is digitized by the computer to pass through the network, and the security of information have attracted an increasing attention. Encryption algorithms become the nucleus of information security, and the overall security of the algorithm is also increasingly becoming a key study of information security. The rapid development of information technology has promoted the development of cipher, so new encryption algorithms appear endless. Symmetric ciphers became one important content of the current research in the field of cryptography,and it is irreplaceable compared with other cryptographic techniques in protecting the security of data in their storage and transmission process. The birth of AES block cipher algorithm has re-attracted people’s attention, boarded the "big stage" of the cipher studying. The main topic of this paper discussed and analyzed is to focus on the important grouping cryptography algorithm-IDEA encryption algorithm.In this paper, we have a complete design for a symmetric cryptosystem that IDEA algorithm encryption and decryption module with the use of FPGA technology. Firstly, IDEA algorithm overall learning and understanding, based on the basic principle of this algorithm, a detailed analysis of its encryption and decryption processes were carried out. According to IDEA encryption and decryption algorithm processes, using the top-down design method we divided cryptographic chip into modules for designing and simulating. Key generation module is responsible for transforming the original key into sub-keys needed for the algorithm and store operations; The control module is to generate a corresponding control signal according to the state change; The main fuction of the module operation is the achievement of round structure, completing a variety of iteration, and addressing the problem to achieve hardware circuit of some complex arithmetic of IDEA algorithm. Finally, each module will be integrated into a comprehensive simulation and verification and the system RTL circuit diagram, comprehensive report will be given together. The final results show that the algorithm is able to accurately implement encryption and decryption operations on the FPGA chip with the speed of 1.4Gbps, and it has a certain degree of feasibility study.