Design Of Low-voltage Power Line Carrier Communication System

Low-voltage Power Line Carrier Communication is a kind of special communication mode using the current low voltage supply network circuitry as an information transmission medium. LPLC is a more and more extensive application with the advantages of no new line, easy installation and low cost. In the 21st century, LPLC has made a great breakthrough in various fields, especially in monitoring system and meter reading system.This paper describes a LPLC system and also discusses the key techniques in common use. This paper presents the overall design schemes which meet the functional requirements with its specific function of remote transport and data acquisition. And then conducts a detailed analysis of the hardware circuit and software design. In hardware designing, the ARM7 series single chip microcomputer is chosen as the MCU of the system, FPGA is used as the spread spectrum and modulation chip, all of which are the component units of the power line communication. The hardware circuit modules mainly contains the MCU function circuit, spread spectrum and modulation circuit, carrier input and output circuit, data acquisition circuit, power supply circuit, etc. Software parts mainly consist of the MCU software design, spread spectrum and modulation software design. MCU software design involves encryption software design, implementation of embedded Low Density Parity Check codes, data acquisition and the definition of data frame format in transmission. Spread spectrum and modulation software design include the implementation of DSSS and 2FSK modulation. This paper also focuses on system function and performance in the aspect of its system consumption, the range of operating voltage, data acquisition and the bit error rate of system, all of which can achieve the attributes of security, reliability, efficient data transmission in practical application.The following system develops two main points in software design. Firstly, in spread spectrum and modulation software design, demodulation and despreading of DSSS execute at the same time, which is beneficial to reduce the resource share of FPGA and improve signal anti-jamming ability during the transmission in channel. Secondly, the system combines the despreading of DSSS with LDPC decoding by using the continuous signal after coherent despreading as LDPC codes, which solves the hard technological problem of handling floating point digits in FPGA, and avoid the use of A/D conversion, thus it reduce hardware cost of the system and on this basis achieve the stable channel coding. In the future, we can also coordinate the reliability and effectiveness by changing the cycle of LDPC codes.